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WB JECA MCA Previous Year Questions (PYQs)

WB JECA MCA Computer Architecture PYQ

WB JECA MCA PYQ
In DMA transfers, the required signals and addresses are given by the ____.





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2024 PYQ

Solution

Solution: In Direct Memory Access (DMA), the DMA controller takes over bus control to put addresses/control signals on the bus, freeing the CPU.
Answer: (C) DMA controllers
WB JECA MCA PYQ
If there are 32 segments each of size 1K bytes, then the logical address should have





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2024 PYQ

Solution

Solution: 32 segments ⇒ segment bits = $\log_2 32 = 5$. Size = 1 KB ⇒ offset bits = $\log_2 1024 = 10$.
Total address bits $= 5 + 10 = \boxed{15}$.
Answer: (D) 15 bits
WB JECA MCA PYQ

__________ interrupt may happen due to power failure.






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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2023 PYQ

Solution

Power failure ⇒ Hardware interrupt.
WB JECA MCA PYQ

11. Address of the next instruction to be executed is specified by ______________.

(A) MBR   (B) MAR   (C) PSW   (D) PC






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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2023 PYQ

Solution

Explanation: The Program Counter (PC) holds the address of the next instruction to be fetched and executed.
WB JECA MCA PYQ

12. Auxiliary memory is also known as ______________ memory.

(A) Primary   (B) Secondary   (C) Binary   (D) Quad






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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2023 PYQ

Solution

Explanation: Auxiliary storage refers to secondary memory (e.g., HDD, SSD, tapes) used for non-volatile, large-capacity storage.

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