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WB JECA MCA Previous Year Questions (PYQs)

WB JECA MCA Computer Organization And Architecture (COA) PYQ


WB JECA MCA PYQ
A system has a 16-bit data bus and a 20-bit address bus. What is the maximum amount of data (in bytes) the system can directly address in memory?





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2025 PYQ

Solution

Address bus = 20 bits → $2^{20}$ addresses → 1 MB memory.

WB JECA MCA PYQ
Which of the following is the correct sequence of stages in a basic instruction pipeline?





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2025 PYQ

Solution

Standard pipeline: Fetch, Decode, Execute.

WB JECA MCA PYQ
________ contains firmware that boots the system.





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2025 PYQ

Solution

ROM stores firmware (BIOS).

WB JECA MCA PYQ
Which of the following is not a valid characteristic of SRAM?





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2025 PYQ

Solution

SRAM does not require refreshing.

WB JECA MCA PYQ
The sequence of events that happen during a typical fetch operation is





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2025 PYQ

Solution

Correct fetch sequence includes MDR before IR.

WB JECA MCA PYQ
A computer with 32 bit wide data bus uses 4K × 8 static RAM memory chips. The smallest memory of this computer is





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WB JECA MCA Previous Year PYQ WB JECA MCA JECA MCA 2025 PYQ

Solution

Need 4 chips → 4K×32 = 16KB.


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